1. Field of the Invention
The instant disclosure relates to a method of manufacturing a semiconductor integrated circuit; in particular, to a method of manufacturing a high aspect ratio isolation structure without voids or seams.
2. Description of Related Art
In semiconductor manufacturing, being more integrated and highly dense are the trend. For satisfying the desired integration and density, the component scale on the semiconductor wafer are reduced to deep submicron and further shrinking is expected. The shrinking components on the wafer lead to ever minimizing layout. For example, the width and interval of the crosslinked wires, the interval and diameter of contact cavity and surface geometric layout are all affected. Typically, reducing the size of the insulation region between the components on the wafer also contributes to device miniaturization.
Currently local oxidation of silicon (LOCOS) and shallow trench isolation (STI) are conventional processing to form a suitable isolation structure between the components on the wafer. STI processing is more popular because the resulting isolation region is smaller and the substrate remains even after processing.
In the conventional STI processing, silicon dioxide and the other insulation materials fill the shallow trench by high density plasma chemical vapor deposition (HDP-CVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). Following the reduced scale, the aspect ratio of the to-be-filled shallow trench is higher. The abovementioned processing may fail to accomplish filling under such small scale. This issue is addressed by using spin-on-dielectric (SOD), also known as spin-on glass (SOG), to precipitate SOD materials in the high aspect ratio shallow trench.
However, the conventional processing for filling SOD materials to in the shallow trench does not provide full solution to the problems faced in this arena.
When the aspect ratio of the shallow trench increases, the insulating materials filled by HDP-CVD processing easily result in void formation. The voids is formed due to poor step coverage and the yield rate is reduced accordingly.
Please refer to FIG. 1 showing a conventional isolation structure 1′. The inner wall of a shallow trench 10′ is hydrophobic. When hydrophilic SOD materials 20′ are filled by the SOD processing to the shallow trench 10′, the high surface tension of the inner wall of the shallow trench 10′ easily causes low fluidity of the SOD materials 20′. As a result, voids are formed in the shallow trench 10′ and affect the yield rate.
In general, the density of silicon dioxide formed by the SOD materials is lower and therefore the subsequent processing for example, dry etching or wet etching, has higher etching rate. In addition, the conversion of SOD materials requires water vapor dispersion therein. The poor dispersion rate is one of the reasons for low density. Hence, in the subsequent hydrofluoric acid washing, SOD materials are prone to erosion and yield rate decreases.
To increase semiconductor component yield rate, the inventor strives via associated experience and research including experimental evidences and evaluation. The instant disclosure, which can effectively improve the limitation described above, is provided.